#ifndef STM32F1_USART_H_
#define STM32F1_USART_H_

#include "iodef.h"

typedef struct {
        __IO uint32_t SR;
        __IO uint32_t DR;
        __IO uint32_t BRR;
        __IO uint32_t CR1;
        __IO uint32_t CR2;
        __IO uint32_t CR3;
        __IO uint32_t GTPR;
}usart_reg_t;

#define USART_SR_PE            _BIT(0)       /* Parity Error */
#define USART_SR_FE            _BIT(1)       /* Framing Error */
#define USART_SR_NE            _BIT(2)       /* Noise Error Flag */
#define USART_SR_ORE           _BIT(3)       /* OverRun Error */
#define USART_SR_IDLE          _BIT(4)       /* IDLE line detected */
#define USART_SR_RXNE          _BIT(5)       /* Read Data Register Not Empty */
#define USART_SR_TC            _BIT(6)       /* Transmission Complete */
#define USART_SR_TXE           _BIT(7)       /* Transmit Data Register Empty */
#define USART_SR_LBD           _BIT(8)       /* LIN Break Detection Flag */
#define USART_SR_CTS           _BIT(9)       /* CTS Flag */

#define USART_CR1_SBK          _BIT(0)       /* Send Break */
#define USART_CR1_RWU          _BIT(1)       /* Receiver wakeup */
#define USART_CR1_RE           _BIT(2)       /* Receiver Enable */
#define USART_CR1_TE           _BIT(3)       /* Transmitter Enable */
#define USART_CR1_IDLEIE       _BIT(4)       /* IDLE Interrupt Enable */
#define USART_CR1_RXNEIE       _BIT(5)       /* RXNE Interrupt Enable */
#define USART_CR1_TCIE         _BIT(6)       /* Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE        _BIT(7)       /* TXE Interrupt Enable */
#define USART_CR1_PEIE         _BIT(8)       /* PE Interrupt Enable */
#define USART_CR1_PS           _BIT(9)       /* Parity Selection */
#define USART_CR1_PCE          _BIT(10)      /* Parity Control Enable */
#define USART_CR1_WAKE         _BIT(11)      /* Wakeup method */
#define USART_CR1_M            _BIT(12)      /* Word length */
#define USART_CR1_UE           _BIT(13)      /* USART Enable */

#define USART_CR2_ADD_MASK     _VALUE(0, 0xF)
#define USART_CR2_LBDL         _BIT(5)       /* LIN Break Detection Length */
#define USART_CR2_LBDIE        _BIT(6)       /* LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL         _BIT(8)       /* Last Bit Clock pulse */
#define USART_CR2_CPHA         _BIT(9)       /* Clock Phase */
#define USART_CR2_CPOL         _BIT(10)      /* Clock Polarity */
#define USART_CR2_CLKEN        _BIT(11)      /* Clock Enable */

#define USART_CR2_STOP_MASK    _VALUE(12, 0x3)
#define USART_CR2_STOP_1       _VALUE(12, 0)
#define USART_CR2_STOP_0_5     _VALUE(12, 1)
#define USART_CR2_STOP_1_5     _VALUE(12, 3)
#define USART_CR2_STOP_2       _VALUE(12, 2)

#define USART_CR2_LINEN        _BIT(14)

#define USART_CR3_EIE          _BIT(0)       /* Error Interrupt Enable */
#define USART_CR3_IREN         _BIT(1)       /* IrDA mode Enable */
#define USART_CR3_IRLP         _BIT(2)       /* IrDA Low-Power */
#define USART_CR3_HDSEL        _BIT(3)       /* Half-Duplex Selection */
#define USART_CR3_NACK         _BIT(4)       /* Smartcard NACK enable */
#define USART_CR3_SCEN         _BIT(5)       /* Smartcard mode enable */
#define USART_CR3_DMAR         _BIT(6)       /* DMA Enable Receiver */
#define USART_CR3_DMAT         _BIT(7)       /* DMA Enable Transmitter */
#define USART_CR3_RTSE         _BIT(8)       /* RTS Enable */
#define USART_CR3_CTSE         _BIT(9)       /* CTS Enable */
#define USART_CR3_CTSIE        _BIT(10)      /* CTS Interrupt Enable */

#define USART_GTPR_PSC_MASK    _VALUE(0, 0xFF)
#define USART_GTPR_PSC(n)      _VALUE(0, (n))

#define USART_GTPR_GT_MASK     _VALUE(8, 0xFF)
#define USART_GTPR_GT(n)       _VALUE(8, (n))


#endif /* STM32F1_USART_H_ */
